In a NAND flash memory, a multi-level-cell technique or storing data of two or more bits in one cell has been widely used in order to reduce bit costs. Further, to reduce the chip size, down-scaling of memory cells is progressing. Under these circumstances, spreading of a threshold voltage distribution of memory cells due to interferences between adjacent cells, and random noise such as read noise and program noise is significant, and it has become more difficult to form a threshold voltage distribution of memory cells in a small range.
A reading error easily occurs when a distance between adjacent threshold-voltage distributions is small. In this case, an improved error correction technique, that is, an ECC (Error-correcting code) technique, is necessary to prevent a reading error. That is, the ECC technique having a high error-correction rate is necessary for down-scaled memory cells using a multi-level-cell technique. In a NAND flash memory, data writing and data reading are performed in a page unit. Conventionally, a unit of error correction is closed within one page. However, according to a recent improved ECC technique, a reading error is sometimes corrected in a unit extended to multiple pages, in order to increase the error correction rate. For example, in the case of an eight-level-cell technique, that is, when a memory cell stores 3-bit data, a group of data extended to three pages is corrected as one unit. By reading the whole pages corresponding to the number of bits stored in each memory cell, a threshold voltage level to which each memory cell belongs to can be specified. Data in a certain memory cell is erroneously detected as data of an adjacent threshold-voltage level with higher probability. Therefore, an improved ECC correction can be achieved by using information about a threshold voltage distribution to which data belongs to.
However, when the unit of ECC correction is extended to multiple pages, these pages need to be read out individually, and thus it takes a long time to read the data out.
To improve writing performance, a batch writing scheme (a full-sequence writing system) is sometimes used in a multi-value NAND flash memory. A four-level-cell NAND flash memory stores 2-bit information in a memory cell by forming four threshold-voltage distributions. In a conventional writing scheme, four threshold-voltage distributions extended to two pages are formed in 2 steps. That is, two threshold-voltage distributions are formed first in writing a lower page, and then final four threshold-voltage distributions are formed in writing an upper page. In the full-sequence writing scheme, the four threshold-voltage distributions corresponding to two pages are formed at one time in a one-time write operation. In this case, before starting a write operation, 2-bit data to be stored in each memory cell needs to be transferred to writing-data latch circuits in advance. In this case, multiple pages also need to be individually transferred, and thus this data transfer takes a long time.